The present invention relates to a memory device, and more particularly, to a circuit and method for testing the memory device in parallel.
Generally, in the memory device such as a dynamic random access memory (DRAM), a read and write operation of data should be performed accurately. For the accurate read and write operation, even one failed cell is not allowed on chip.
However, as tens of millions of cells are integrated on a chip along with the very large scaled integration trend, despite of the development of the fabricating process, the possibility of existing the failed cell is relatively higher. The reliability of the memory device can not be secured unless an accurate test on this failed cell is performed.
When testing the memory device, it is desirable to test on the tens of millions of cells speedily as well as reliably. Especially, reduction of time for developing and testing the memory device until a shipment thereof effects on a product cost. Therefore, it is a very important issue to reduce the time taken for testing the memory device for the purpose of a competition between manufacturing companies and the efficiency in production.
Generally, when performing a test on each cell of a semiconductor memory device, it takes a long time, which causes an increase in the cost.
Therefore, a parallel test is used in order to reduce the test time. In the parallel test, the same data is recorded in a plurality of cells, and the data recorded in the cells are read out in parallel and checked to determine whether the data outputted from the cells are identical to each other, that is, whether the data are correctly recorded in and read out from cells.